In a high speed computing system, a large number of transactions (e.g., memory read, memory write, etc.) are generated by internal processors connected together by a processor bus. These transactions are communicated to devices on another bus through a core electronic complex known as a “chipset.” For each transaction, the chipset generates a unique transaction identifier (ID) and then manages the transaction through its expiration.
More particularly, the chipset includes a transaction ID generator, which produces each transaction ID, and a transaction processor, which assigns the transaction ID to the transaction and thereafter manages and tracks the transaction. It is important that the chipset assign the transaction ID to each transaction immediately after the transaction is received by the chipset so that the transaction may be used without substantial latency.
Latency nonetheless occurs because the transaction processor and the transaction ID generator are not in close proximity to one another and do not operate within the same clocking domain: the transaction processor operates within the clock domain associated with the processor bus; the transaction ID generator operates within a different clocking domain associated with the chipset. Within any one clock domain, a signal is typically synchronized with a clock that defines its validity. When the signal transitions from one clock domain to another clock domain, the signal is synchronized to match the clock of the destination clock domain. In the chipset, a synchronizer operates to synchronize transaction signals across the two time domains, and, in so doing, incurs a time delay that increases latency in generating the transaction ID.
In addition, the transaction ID generator requires a finite time period to generate a new transaction ID, further increasing latency. The time period is determined, in part, by the time it takes the transaction ID generator to specify a new transaction ID that does not conflict with an active transaction ID, since the transaction ID generator may only generate a maximum number of unique transaction IDs. The time period is further impacted by the time it takes the transaction ID generator to manage a transaction table that stores information relating to the identified transaction.
The transaction ID generator also generates transaction IDs sequentially, and only one transaction ID is made available to the transaction processor at any one time. After assigning a transaction ID to a transaction, the transaction processor must therefore wait for a new transaction ID from the transaction ID generator before processing new transactions, resulting in additional latency in the generation of transaction IDs for new transactions.
Since the state of the art high speed computing system utilizes multiple high speed busses, the allowable time to generate each transaction ID is reduced; an improvement to system performance therefore needs to address latency in generating the transaction ID.